This web page takes a more in-depth look on the Raspberry Pi memory hierarchy. Each stage of the memory hierarchy has a capability and speed. Capacities are relatively straightforward to find by querying the working system or studying the ARM1176 technical reference handbook. Velocity, nevertheless, just isn't as simple to find and Memory Wave Workshop must normally be measured. I exploit a easy pointer chasing approach to characterize the habits of every degree in the hierarchy. The technique additionally reveals the habits of Memory Wave Workshop-related efficiency counter occasions at each stage. The Raspberry Pi implements 5 ranges in its memory hierarchy. The degrees are summarized in the desk below. The highest stage consists of digital memory pages which might be maintained in secondary storage. Raspbian Wheezy keeps its swap house within the file /var/swap on the SDHC card. This is enough area for 25,600 4KB pages. You are allowed as many pages as will match into the preallocated swap area.
The Raspberry Pi has both 256MB (Model A) or 512MB (Mannequin B) of major memory. That is sufficient area for 65,536 pages or 131,072 physical pages, if all of major memory were accessible for paging. It isn’t all accessible for user-area programs as a result of the Linux kernel needs area for Memory Wave its personal code and data. Linux also helps large pages, however that’s a separate topic for now. The vmstat command displays details about virtual memory usage. Please refer to the man web page for Memory Wave Workshop utilization. Vmstat is a good instrument for troubleshooting paging-related performance points since it exhibits page in and out statistics. The processor in the Raspberry Pi is the Broadcom BCM2835. The BCM2835 does have a unified degree 2 (L2) cache. Nevertheless, the L2 cache is dedicated to the VideoCore GPU. Memory references from the CPU facet are routed across the L2 cache. The BCM2835 has two degree 1 (L1) caches: a 16KB instruction cache and a 16KB data cache.
Our evaluation beneath concentrates on the data cache. The data cache is 4-way set associative. Every manner in an associative set stores a 32-byte cache line. The cache can handle up to four lively references to the same set without battle. If all four ways in a set are legitimate and a fifth reference is made to the set, then a conflict happens and one of the four ways is victimized to make room for the brand new reference. The data cache is nearly listed and physically tagged. Cache strains and tags are stored separately in DATARAM and TAGRAM, Memory Wave respectively. Digital deal with bits 11:5 index the TAGRAM and DATARAM. Given a 16KB capacity, 32 byte lines and four ways, there should be 128 sets. Digital handle bits 4:0 are the offset into the cache line. The information MicroTLB translates a virtual handle to a bodily handle and sends the bodily deal with to the L1 data cache.
The L1 data cache compares the bodily address with the tag and determines hit/miss status and the right manner.