In computing, interleaved memory is a design which compensates for the comparatively gradual velocity of dynamic random-entry memory (DRAM) or core memory, by spreading memory addresses evenly across memory banks. That manner, contiguous memory reads and writes use each memory financial institution in turn, leading to higher memory throughput due to lowered ready for memory banks to develop into ready for the operations. It is totally different from multi-channel memory architectures, primarily as interleaved memory doesn't add more channels between the primary memory and the memory controller. Nonetheless, channel interleaving can be possible, for instance in freescale i.MX6 processors, which allow interleaving to be done between two channels. With interleaved memory, memory addresses are allotted to each memory financial institution in flip. For instance, in an interleaved system with two memory banks (assuming word-addressable memory), if logical address 32 belongs to bank 0, then logical handle 33 would belong to bank 1, logical handle 34 would belong to bank 0, and Memory Wave so forth. An interleaved memory is claimed to be n-approach interleaved when there are n banks and memory location i resides in bank i mod n.

Interleaved memory results in contiguous reads (which are widespread each in multimedia and execution of packages) and contiguous writes (that are used frequently when filling storage or communication buffers) actually utilizing every memory financial institution in flip, as an alternative of utilizing the identical one repeatedly. This results in considerably larger memory throughput as each bank has a minimal waiting time between reads and writes. Principal memory (random-entry memory, RAM) is usually composed of a group of DRAM memory chips, where various chips might be grouped together to type a memory financial institution. It is then doable, with a memory controller that helps interleaving, to lay out these memory banks in order that the memory banks might be interleaved. Information in DRAM is saved in models of pages. Every DRAM bank has a row buffer that serves as a cache for accessing any web page within the financial institution. Before a web page within the DRAM financial institution is learn, it's first loaded into the row-buffer.

If the web page is immediately learn from the row-buffer (or a row-buffer hit), it has the shortest memory entry latency in one memory cycle. If it's a row buffer miss, which can also be known as a row-buffer battle, it's slower because the new web page must be loaded into the row-buffer before it's read. Row-buffer misses occur as entry requests on completely different memory pages in the same financial institution are serviced. A row-buffer conflict incurs a substantial delay for a memory entry. In contrast, memory accesses to completely different banks can proceed in parallel with a excessive throughput. The problem of row-buffer conflicts has been well studied with an effective answer. The dimensions of a row-buffer is often the dimensions of a memory web page managed by the operating system. Row-buffer conflicts or misses come from a sequence of accesses to distinction pages in the same Memory Wave bank. The permutation-primarily based interleaved memory method solved the issue with a trivial microarchitecture value.

Solar Microsystems adopted this the permutation interleaving technique shortly of their products. This patent-free technique may be discovered in lots of industrial microprocessors, such as AMD, Intel and NVIDIA, for embedded programs, laptops, desktops, and enterprise servers. In traditional (flat) layouts, memory banks will be allotted a contiguous block of memory addresses, which is very simple for the memory controller and offers equal performance in fully random access scenarios, when compared to performance levels achieved through interleaving. Nevertheless, in reality memory reads are rarely random as a consequence of locality of reference, and optimizing for close collectively access provides far better efficiency in interleaved layouts. The best way Memory Wave Routine is addressed has no impact on the entry time for memory places which are already cached, having an impact solely on memory locations which should be retrieved from DRAM. Zhao Zhang, Zhichun Zhu, Memory Wave Routine and Xiaodong Zhang (2000). A Permutation-based Web page Interleaving Scheme to scale back Row-buffer Conflicts and Exploit Information Locality. Division of Computer Science and Engineering, College of Engineering, Ohio State University. Mark Smotherman (July 2010). "IBM Stretch (7030) - Aggressive Uniprocessor Parallelism".

Edit

Pub: 31 Aug 2025 03:37 UTC

Views: 3