Excessive Bandwidth Memory Wave (HBM) is a computer Memory Wave Audio interface for 3D-stacked synchronous dynamic random-entry memory (SDRAM) initially from Samsung, AMD and SK Hynix. RAM in upcoming CPUs, and Memory Wave Audio FPGAs and in some supercomputers (such because the NEC SX-Aurora TSUBASA and Fujitsu A64FX). HBM achieves increased bandwidth than DDR4 or GDDR5 while utilizing less energy, and in a considerably smaller kind issue. That is achieved by stacking up to eight DRAM dies and an optional base die which might include buffer circuitry and take a look at logic. The stack is commonly linked to the memory controller on a GPU or CPU by a substrate, reminiscent of a silicon interposer. Alternatively, the memory die could possibly be stacked directly on the CPU or GPU chip. Throughout the stack the dies are vertically interconnected by through-silicon vias (TSVs) and microbumps. The HBM technology is comparable in precept however incompatible with the Hybrid Memory Cube (HMC) interface developed by Micron Technology. HBM memory bus is very large compared to other DRAM recollections similar to DDR4 or GDDR5.

An HBM stack of 4 DRAM dies (4-Hello) has two 128-bit channels per die for a total of eight channels and a width of 1024 bits in whole. A graphics card/GPU with four 4-Hi HBM stacks would subsequently have a memory bus with a width of 4096 bits. Compared, the bus width of GDDR recollections is 32 bits, with sixteen channels for a graphics card with a 512-bit memory interface. HBM helps as much as 4 GB per package deal. The larger number of connections to the memory, relative to DDR4 or GDDR5, required a new methodology of connecting the HBM memory to the GPU (or other processor). AMD and Nvidia have each used objective-built silicon chips, called interposers, to attach the Memory Wave and GPU. This interposer has the added advantage of requiring the memory and processor to be physically close, decreasing memory paths. Nonetheless, as semiconductor gadget fabrication is significantly dearer than printed circuit board manufacture, this adds cost to the final product.

The HBM DRAM is tightly coupled to the host compute die with a distributed interface. The interface is divided into impartial channels. The channels are completely unbiased of one another and should not essentially synchronous to one another. The HBM DRAM uses a large-interface architecture to achieve excessive-pace, low-energy operation. Every channel interface maintains a 128-bit information bus operating at double information charge (DDR). HBM supports switch charges of 1 GT/s per pin (transferring 1 bit), yielding an total bundle bandwidth of 128 GB/s. The second generation of High Bandwidth Memory, HBM2, additionally specifies as much as eight dies per stack and doubles pin switch rates up to 2 GT/s. Retaining 1024-bit extensive access, HBM2 is able to achieve 256 GB/s memory bandwidth per package deal. The HBM2 spec allows up to 8 GB per package. HBM2 is predicted to be especially helpful for efficiency-delicate client purposes such as digital actuality. On January 19, 2016, Samsung announced early mass production of HBM2, at up to 8 GB per stack.

In late 2018, JEDEC announced an update to the HBM2 specification, offering for increased bandwidth and capacities. Up to 307 GB/s per stack (2.5 Tbit/s efficient knowledge rate) is now supported within the official specification, although products operating at this pace had already been accessible. Additionally, the update added support for 12-Hello stacks (12 dies) making capacities of up to 24 GB per stack potential. On March 20, 2019, Samsung introduced their Flashbolt HBM2E, featuring eight dies per stack, a transfer rate of 3.2 GT/s, offering a total of sixteen GB and 410 GB/s per stack. August 12, 2019, SK Hynix introduced their HBM2E, that includes eight dies per stack, a switch price of 3.6 GT/s, providing a total of 16 GB and 460 GB/s per stack. On July 2, 2020, SK Hynix announced that mass manufacturing has begun. In October 2019, Samsung introduced their 12-layered HBM2E. In late 2020, Micron unveiled that the HBM2E customary would be updated and alongside that they unveiled the next standard often called HBMnext (later renamed to HBM3).

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Pub: 13 Aug 2025 19:14 UTC

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